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A7101
Preliminary
Document Title 2.4GHz FSK Transceiver Revision History
Rev. No.
0.0 0.1
2.4GHz FSK Transceiver
History
Initial issue Modify current consumption, Tx output power, sensitivity, RSSI range, frequency deviation, data rate, SPI interface, and pin description.
Issue Date
August 2, 2002 October 16, 2002
Remark
Preliminary Preliminary
0.2 0.3 0.4
Modify X'TAL Settling Time, Tx output power (Hi power) Application Circuit, and delete X'TAL accuracy Modify Tx output power (Hi power) Modify data rate and calibration mode
June 9, 2003 Dec. 30 2003 March 10, 2004
Preliminary Preliminary Preliminary
Important Notice: AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMIC products in such applications is understood to be fully at the risk of the customer.
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AMIC Technology, Corp.
A7101
Preliminary Typical Applications
Wireless Mouse and Keyboard 2.4GHz ISM Band Communication System Two way wireless Transceiver Wireless toy Wireless Modem
2.4GHz FSK Transceiver
General Description
The A7101 is a monolithic CMOS integrated circuit intended for use as a low cost FSK transceiver in wireless applications. The device is provided in 48-lead plastic QFN7X7 packaging and is designed to function as a complete FSK transceiver. It is intended for wireless applications in the 2.4GHz to 2.5GHz ISM band. This chip features a fully programmable frequency synthesizer with integrated VCO circuitry.
Pin Configurations
CAP2_AFC CAP1_AFC CAP3_AFC
LPFOUT
EN_AFC
CMPVIP
LPFINN
LPFINP
TANK1
TANK2
48
47
46
45
44
43
42
41
38
37
40
39
MUTE
RSSI
VDD_A RXDATA BR_RX NC RFIO BP_BUF TXDATAIN XTAL1 XTAL2 XTALOUT CAPSW BP_REG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32
LIM2INN LIM2INP LIM1OUT LIM1INN LIM1INP MIXOUT VDD_VCO BP_VCO VT BR_VCO CHPOUT LD
A7101
31 30 29 28 27 26 25
VDD_D
SPI_CLOCK
EN_REG
LVOUT
SPI_LATCH
MODSEL0
Figure 1. QFN Package Top View
SPI_DATA
MODSEL1
VUOT
LVIN
REGFB
VIN
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A7101 Block Diagram
34
LIM1OUT
35
LIM2INP
36
LIM2INN MUTE
37
RSSI
38
39
TANK2
40
LPFINP TANK1
41
LPFINN
42
43
LPFOUT
48
CMPVIP
2
RXDATA
33 32 31
LIM1INN LIM1INP DEMOD
Data Slicer
LPF Integrator
EN_AFC
Limiter1
MIXOUT
Limiter2
47 46 45 44 29 28
LNA
CAP2_AFC CAP1_AFC
5
RFIO
PA
CAP3_AFC
VCO
7 11 8
TXDATAIN CAPSW
BP_VCO
FSK Modulation Circuit
Buffer
VT
XTAL1
/ 32
OSC
33
Bias
BR_VCO
27
CHPOUT
9
XTAL2
Counter
Phase Detector Charge Pump
26 25
LD
10
XTALOUT
21
REGFB
Voltage Regulator & Low voltage detector
SPI_DATA EN_REG BP_REG
SPI
SPI_CLOCK SPI_LATCH
Mode Selection
MODSEL0 MODSEL1
LVOUT
VOUT
LVIN
12
13
14
16
22
VIN
23
17
18
19
20
24
Figure 2. System Block Diagram
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A7101 Specification
Parameter General Storage Temperature Operating Temperature Supply Voltage Current Consumption Transceiver Circuit Active (RX Mode) Active (TX Mode @high power) Active (TX Mode @low power) Stand By Mode Sleep Mode Active @VIN = 3.3V Stand By Description Min. -20 0 2.2 2.5 30 17 14 1.5 5 150 5 Typ. Max. 70 50 5 Unit C C V mA mA mA mA A A A
Current Consumption Embedded Regulator Phase Locked Loop Reference Frequency X'TAL Settling Time Operation Frequency Number of Channels PLL Settling Time RF Front End (TX mode) TX Power RF Output Impedance RF Front End (RX mode) RF Input Impedance Sensitivity Cascaded IIP3 TBM IF Section Intermediate Frequency RSSI Range Modulation / Demodulation Scheme Data rate Frequency Deviation Regulator Supply voltage Output voltage Drop out voltage Load current Battery-Low indicator reference
@12MHz, cap. Load = 20pF @ 2MHz spacing @Loop bandwidth = 100KHz High Power Low Power @2.45GHz @2.45GHz @BER=0.001
4,6,8,10,12,14,16 5 2416~2478 32 150 -6 -16 50 50 -80 -30 10.7
MHz ms MHz s dBm dBm Ohm Ohm dBm dBm MHz dBm
@RF input FSK @ Crystal modulation @ VCO modulation @ Crystal modulation @ VCO modulation
-90
-50
64 100 50 150 5 2.5 0.2 50 1.2
Kbps Kbps KHz KHz V V V mA V
Table 1.
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A7101 RF - Baseband Interface
Pin Number 23 Pin Name VIN GND 7 2 17 18 19 20 24 25 22 13 37 47 TXDATAIN RXDATA SPI_DATA SPI_CLOCK SPI_LATCH MODSEL0 MODSEL1 LD EN_REG LVOUT MUTE EN_AFC Supply voltage. Ground. Transmitter data input. Receiver data output. Data for SPI interface. Clock for SPI interface. Latch for SPI interface. Chip operation mode selection (LSB). Chip operation mode selection (MSB). PLL locked detect Indicator output. Voltage regulator enable pin. Battery-low indicator output. Receiver mute control output pin. AFC circuit control pin. Table 2. Option. Option. Option. Option. Option. Option. Option. Please see Pin Descriptions section for detail. Description Note
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A7101 Pin Descriptions (I: input O: output OD: open drain output)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Symbol VDD_A RXDATA BR_RX NC RFIO BP_BUF TXDATAIN XTAL1 XTAL2 XTALOUT CAPSW BP_REG LVOUT LVIN VDD_D VOUT SPI_DATA SPI_CLOCK SPI_LATCH I/O O I I I O I O O I I O I/OD I I I/O I OD O Analog supply voltage input. Recovered data output. This pin is an open drain output. Receiver band gap bias output. Connect to external resistor to set bias current. This pin must be open. RF input/output port. Noise bypass. Connect to external noise rejection capacitor. Transmitter data input. Colpitts crystal oscillator node 1. Connect to external feedback capacitor. Colpitts crystal oscillator node 2. Connect to external feedback capacitor. Buffered crystal oscillator output. Modulation switch input. Regulator band gap bypass output. Connect to external noise rejection capacitor. Typical output voltage is 1.2V. Battery-Low voltage indicator output. This pin is active low when LVIN is below BP_REG voltage level. Input for battery-low voltage indicator. The indicator compares LVIN with the threshold voltage, BP_REG. Digital supply voltage input. Regulator output voltage. Nominal voltage output is 2.5V. Data for SPI interface. This pin operates as an Input pin when SPI is in Write mode. This pin operates as an open drain output when SPI is in Read mode. Clock input for SPI interface. Latch input for SPI interface. Transceiver (embedded regulator is not included) operation mode selection inputs. 20 24 MODSEL0 MODSEL1 MODSEL[1:0] = 00: Sleep mode. Transceiver circuit is turned off. I MODSEL[1:0] = 01: Stand-by mode. X'TAL oscillator is turned on. MODSEL[1:0] = 10: Transmit mode. MODSEL[1:0] = 11: Receive mode. 21 22 23 25 26 27 28 29 30 REGFB EN_REG VIN LD CHPOUT BR_VCO VT BP_VCO VDD_VCO O I I OD O O I O I Output from regulator feedback network. VOUT is set to nominal voltage when this pin is opened. If other voltage is required, connect it to external resistor to adjust VOUT. Voltage regulator enable pin. Signal is active high. Supply voltage for the internal voltage regulator. Output from PLL lock detector. This pin is active high (Open drain) when PLL is locked. Charge-pump output. This pin charges external capacitor to adjust VCO frequency. VCO band gap bias output. Connect to external resistor to set bias current. VCO tuning voltage input. The VCO frequency increases as VT increases. Noise bypass. Connect to external noise rejection capacitor. VCO supply voltage input. Function Description
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A7101 Pin Descriptions (I: input O: output OD: open drain output)(continued)
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol MIXOUT LIM1INP LIM1INN LIM1OUT LIM2INP LIM2INN MUTE RSSI TANK2 TANK1 LPFINP LPFINN LPFOUT CAP3_AFC CAP1_AFC CAP2_AFC EN_AFC CMPVIP I/O O I I O I I OD O I I I I O O O O I I Single-ended Mixer output. First Limiter differential positive input. First Limiter differential negative input. First Limiter single-ended output. Second Limiter differential positive input. Second Limiter differential negative input. Receiver mute control output. Open drain output. This pin is active low when received RF signal is under threshold level. Received Signal Strength Indicator output. RSSI output voltage is inversely proportional to the received RF signal power level. Demodulator Tank 2 input. Demodulator Tank 1 input. Low pass filter differential positive input. Low pass filter differential negative input. Low pass filter single-ended output. Auto frequency control circuit output bypass pin3. Connect to external capacitor. Auto frequency control circuit output bypass pin 1. Connect to external capacitor. Auto frequency control circuit output bypass pin 2. Connect to external capacitor. AFC circuit control input. Signal is active high. Positive input for data slicer. Table 3. Function Description
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A7101 Absolute Maximum Rating*
Parameter Supply voltage range (VDD) Other I/O pins range Maximum input RF level Storage temperature range Table 4. *Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. With respect to GND GND Rating -0.3 to 5.5 -0.3 to VDD+0.3 0 -20 ~ +70 Unit Vdc Vdc dBm C
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A7101 Circuit Description
1. Low Noise Amplifier
The first stage of the receiver is a low noise amplifier. The main function of the LNA is to provide enough gain to overcome noise generated by subsequent stages. In order to make the circuit less sensitive to parasitic parameters, and more tolerant to common mode disturbances, differential pair is used. The LNA operates at very low power consumption with modest 20dB voltage gain. It is internally matched to 50ohm. No other external components are required.
2. RF Mixer
The RF mixer is designed to translate incoming RF signal to intermediate frequency (IF). The mixer is a conventional double balanced Gilbert cell mixer. Its output impedance is matched to 330ohm. A conventional 330ohm ceramic filter should be connected between the mixer and the first limiter to filter out all un-wanted noise.
3. IF Limiter
The IF limiter consists of two stages: The first IF limiter stage consists of 3 differential amplifiers and a single-ended output buffer. The output impedance of the single-ended buffer is matched internally to 330 ohm, permitting direct connection to a 330ohm ceramic filter. A second filter can be connected between the first limiter and the second limiter to increase the receiver selectivity. Minimum input level of approximately 100mVRMS is required at the first limiter to generate a limited signal at the output of the second IF limiter. The first IF limiter provides a gain of approximately 34dB. A by-pass capacitor of 10nF should be used to connect LIM1INN to ground. The second IF limiter consists of 4 differential amplifiers and a differential output buffer. The second IF limiter provides an overall gain of approximately 40 dB. A by-pass capacitor of 10nF should be used to connect LIM2INN to ground. The limiter output is fed directly to the FSK demodulator.
4. Demodulator
The demodulator demodulates the FSK signal. It consists of a quadrature multiplier, external LC tank circuit and a tuning circuit to adjust the tank resonant frequency.
5. Low Pass Filter (LPF)
An internal operational amplifier connected with external RC components makes up the LPF. The bandwidth of LPF can be determined by external RC values.
6. Data Slicer
The data slicer compares the output of low pass filter with internal reference voltage threshold, VREF and provides binary logic signals. The data slicer output is open drain type and will be pull high when data is muted.
7. RESET
When SPI_CLOCK and SPI _LATCH are both held high simultaneously, bit 4 through bit 9 of the Mode Select Register will be reset to "Low" state.
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A7101
8. Serial to Parallel Interface (SPI)
The SPI bus consists of three signals: SPI_DATA, SPI_CLOCK, and SPI_LATCH. This interface is used for external baseband controller to communicate with transmitter's internal data and control registers. The contents of the registers are shown in the following register description sections. After setting SPI_LATCH signal to "Low" state, data on SPI_DATA is shifted into the internal shift register on the rising edge of SPI_CLOCK with MSB going in first. SPI_LATCH should be asserted at the end to latch the data packet into the register according to the address bits, bit 0 through bit 3, for each of the registers. All registers can only be written into except the Status Register which can only be read. When the content of the Status Register need to be fetched by external controller, external baseband controller need to make sure that the address bits are pointing to address location 0x0 for proper read operation. After the address bits are shifted into the SPI interface and latched by asserting SPI_LATCH, the SPI interface will be in Read Mode and the content of the Status Register will be shifted out on SPI_DATA pin. When all 12 status bits have been shifted out, the SPI bus will be put back to Write Mode automatically. A. Register Description
Note: Convention used: 1: Logic level "ONE". 0: Logic level "ZERO". X: Don't care.
Synthesizer Configuration Register I (Write only / Address 0xf) Bit 15 Bit 14 Bit 13 MB6 MB5 MB4 Bit12 MB3 Bit11 MB2 Bit10 MB1 Bit9 MB0 Bit8 MA4 Bit7 MA3 Bit6 MA2 Bit5 MA1 Bit4 MA0 Bit3 1 Bit2 1 Bit 1 1 Bit 0 1
Synthesizer Configuration Register II (Write only / Address 0x7) Bit 15 Bit 14 Bit 13 X MB9 MB8 Bit12 MB7 Bit11 R7 Bit10 R6 Bit9 R5 Bit8 R4 Bit7 R3 Bit6 R2 Bit5 R1 Bit4 R0 Bit3 0 Bit2 1 Bit 1 1 Bit 0 1
Synthesizer Configuration Register I and Synthesizer Configuration Register II control synthesizer frequency settings where MA[4:0]: A counter[4:0], MB[9:0]: B counter[9:0], R[7:0]: R counter[7:0]. Valid range is from 2 to 255. The content of A, B and R registers are in unsigned binary format (i.e., 111112 = 3110). The equation for setting the synthesizer frequency is: (B must be greater than A). fvco = fcrystal * (32*B + A) / R fref =fcrystal / R Crystal Control Register (Write only / Address 0xb) Bit 15 Bit 14 Bit 13 Bit12 Bit11 Bit10 0 DP TXH2 TXH1 TXH0 TXL2 Bit9 TXL1 Bit8 TXL0 Bit7 FX3 Bit6 FX2 Bit5 FX1 Bit4 FX0 Bit3 1 Bit2 0 Bit 1 1 Bit 0 1
DP: Data Polarity. This control bit sets data output polarity. 0: Data is inverted. 1: Normal. TXH[2:0]: Reserved. Must be set to 0x0 for proper operation. TXL[2:0]: Reserved. Must be set to 0x0 for proper operation. FX[3:0]: Reserved. Must be set to 0x0 for proper operation.
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A7101
VCO Control Register (Write only / Address 0x3) Bit 15 Bit 14 Bit 13 VTH2 VTH1 VTH0 Bit12 T1 Bit11 T0 Bit10 HP0 Bit9 CP2 Bit8 CP1 Bit7 CP0 Bit6 VC2 Bit5 VC1 Bit4 VC0 Bit3 0 Bit2 0 Bit 1 1 Bit 0 1
VTH[2:0]: Set VCO tuning voltage range. Valid range is from 0x7 to 0x0. The setting of VTH varies inversely with the tuning voltage range such that when VTH = 0x0 tuning voltage range is from 0.3V to VDD-0.3V and when VTH = 0x7 tuning voltage range is from 1V to VDD-1V. T[1:0]: Reserved. Must be set to 0x0 for proper operation. HP0: RF output power level control. 0: Low power output (-16 dBm). 1: High power output (-6 dBm). CP[2]: Reserved. Must be set to 0x0 for proper operation. CP[1:0]: Charge pump output current control. Valid range is from 0x3 to 0x0. The setting of CP varies linearly with the output current level such that when CP = 0x0 output current = 100uA and when CP = 0x3 output current = 700uA. VC[2:0]: VCO band selection.
RX Control Register (Write only / Address 0xd) Bit 15 Bit 14 Bit 13 T2 T1 T0 Bit12 MT2 Bit11 MT1 Bit10 MT0 Bit9 MTC Bit8 DM4 Bit7 DM3 Bit6 DM2 Bit5 DMI Bit4 DM0 Bit3 1 Bit2 1 Bit 1 0 Bit 0 1
T[2:0]: Reserved. Must be set to 0x3 for proper operation. MT[2:0]: Internal voltage threshold level for mute output (pin 37). Valid range is from 0x7 to 0x0. The setting of MT varies linearly with the voltage reference level such that when MT = 0x0 voltage reference = 1.44V and when MT = 0x7 voltage reference = 0.32V. MTC: RXDATA mute function enable. 0: Disable mute function. 1: Enable mute function. When RSSI output voltage level is higher than the threshold set by MT[2:0], RXDATA becomes inactive and pull high. DM[4:0]: Reference voltage level for demodulator tank center frequency tuning. Valid range is from 0x1f to 0x6. The setting of DM varies with the voltage reference level such that when DM = 0x6 voltage reference = 0.9V and when DM = 0x1f voltage reference = 2.4V. Note: When AFC function is used, set DM[4:0] to 0x0.
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Mode Select Register (Write only / Address 0x5) Bit 15 Bit 14 Bit 13 X X X Bit12 X Bit11 X Bit10 SC1 Bit9 SC0 Bit8 XOE Bit7 CM Bit6 EXTB Bit5 MD1 Bit4 MD0 Bit3 0 Bit2 1 Bit 1 0 Bit 0 1
SC[1:0]: Status Register bit 6 control. Depends on the setting of SC[1:0], bit 6 of the Status Register can represent system error flag, Battery-low detect or PLL lock detect. [1:0] = 10: System Error. [1:0] = 11: Battery-low detect. [1:0] = 0X: PLL lock detect. XOE: Crystal oscillator buffer output enable. 0: Output enable. 1: Output disable. The output will be forced to low level at this setting. CM: Calibration mode setting for VCO band selection. 0: manual calibration mode. Please see application note for detail description. 1: auto calibration mode. EXTB: Operating mode selection. 0: external mode. Operation mode is determined by external pin MODSEL0 and MODSEL1. 1: internal mode. Operation mode is determined by setting of MD[1:0]. MD[1:0]: Internal mode selection. [1:0] = 00: Sleep mode. Transceiver circuit is turned off. [1:0] = 01: Stand-by mode. X'TAL oscillator is turned on. [1:0] = 10: Transmit mode. [1:0] = 11: Receive mode. Status Register (Read only / Address 0x0) SR15 SR14 SR13 SR12 SR11 SR10 X X X X X X SR9 X SR8 X SR7 X SR6 S/B/P SR5 X SR4 X SR3 0 SR2 0 SR1 0 SR0 0
S/B/P: Depends on the setting of SC[1:0] in Mode Select Register, this bit can be used to reflect the status of System Error, Battery-low detect or PLL lock detect. System Error: 0: Normal; 1: Error. Battery-low detect: 0: Battery supply voltage below threshold. 1: Normal. PLL lock detect: 0: Unlock. 1: Lock. SR[3:0] address bits.
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B. SPI Timing Diagram
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
Bit5 Bit4
Bit3
Bit2 Bit1 Bit0
VH VI
SPI_DATA
SPI_CLOCK
tCS tCH tCWH tCWL tEW tES
SPI_LATCH
Figure 3. SPI WRITE mode timing diagram After reading 12 bits, SPI is set to write mode
SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 SR11 SR12 SR13 SR14 SR15 Bit15 Bit14
SPI_DATA
SPI_CLOCK
SPI_LATCH Figure 4. SPI READ mode timing diagram
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C. SPI Timing Specification Value Symbol VH Vl tCE tCH tCWH tCWL tES tEW Parameter The High level of voltage The low level of voltage SPI_DATA to SPI_CLOCK setup time SPI_CLOCK to SPI_DATA hold time SPI_CLOCK pulse width high SPI_CLOCK pulse width low SPI_CLOCK to SPI_LATCH setup time SPI_LATCH pulse width Conditions Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Table 5. 50 10 50 50 50 50 Min VCC-0.4 0.4 Typ Max V V ns ns ns ns ns ns Units
9. PLL Section
The sub-block diagram of PLL is shown in the following: Input from reference crystal OSC. M Counter VCO input PRESCALER 32/33 R Counter 8 bit
A Counter 5 bit B Counter 10 bit
Phase Detector CHPOUT Charge Pump
Control Logic
Figure 5. Phase Lock Loop Block Diagram
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A. M Counter The M counter consists of a 32/33 pre-scalar, a 5-bit A counter and a 10-bit B counter (where M = B*32+A). B. A and B counters A and B counters can be programmed through the Synthesizer Configuration Register I and II. The corresponding relations between the division ratio counters and Synthesizer Configuration Register are shown in the following table: M counter (DEC) 24000 24001 . 24031 24032 24033 . 24063 24064 . . 24992 24993 24994 24995 24996 24997 24998 24999 25000 C. R counter R counter division R (DEC) 2 3 . 100 101 102 . 120 . 255 R counter R4 R3 0 0 0 0 . . 0 0 0 0 0 0 . . 1 1 . . 1 1 Table 7. B counter A counter B counter (binary) A counter (binary) (DEC) (DEC) MB9 MB8 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 MA4 MA3 MA2 MA1 MA0 750 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 750 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . 750 31 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 751 0 1 0 1 1 1 0 1 1 1 1 0 0 0 0 0 751 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 1 . . . . . . . . . . . . . . . . . 751 31 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 752 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 781 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 1 781 2 1 1 0 0 0 0 1 1 0 1 0 0 0 1 0 781 3 1 1 0 0 0 0 1 1 0 1 0 0 0 1 1 781 4 1 1 0 0 0 0 1 1 0 1 0 0 1 0 0 781 5 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 781 6 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 781 7 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 781 8 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 Table 6.
R7 0 0 . 0 0 0 . 0 . 1
R6 0 0 . 1 1 1 . 1 . 1
R5 0 0 . 1 1 1 . 1 . 1
R2 0 0 . 1 1 1 . 0 . 1
R1 1 1 . 0 0 1 . 1 . 1
R0 0 1 . 0 1 0 . 1 . 1
Note: Valid range of R counter is from 2 to 255.
The equation for setting the synthesizer frequency is: fvco = fcrystal X (32 X B + A) / R (B must be greater than A).
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D. Phase Frequency Detector (PFD) and Charge Pump Phase Frequency Detector takes inputs from R counter and M counter, and produces an output proportional to the phase and frequency difference. The following shows a simplified schematic:
VDD
D1 Q1
DN
VCK
CLR Delay Element
Charge Pump
CHPOUT
VDD RCK
CLR D1 Q1
UP
Figure 6. Phase Detector Block Diagram
The PFD output waveform is shown below.
VCK
RCK
UP
DN
CHPOUT
LD
Locked
Figure 7. The PFD output waveform
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10. Crystal Oscillator and FSK modulation Section
As shown in the following figure, it is a Colpitts type Crystal oscillator(XOSC). The FSK modulation is achieved by switching the external capacitor CX in the XOSC circuit. External Internal Output buffer XTALOUT XTAL1
Cx XTAL2
TXDATAIN
CAPSW
Figure 8. Crystal Oscillator and FSK modulation Circuit
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12.Chip setup procedure:
(1) Auto calibration: For Transmitter Operation Step 1: Supply DC voltage to Pin 23, VIN. Step 2: Set Pin 20, MODSEL0 and Pin 24, MODSEL1 to logic 0 (ground) to ensure the IC is operating in external sleep mode after reset. Step 3: Reset IC by setting Pin 18, SPI_CLOCK and Pin 19, SPI _LATCH to logic high simultaneously for more than 1 us. Step 4: Setup IC's internal control registers by configuring the followings: Synthesizer Configuration Register I, Synthesizer Configuration Register II, Crystal Control Register, and VCO Control Register. All registers should be written to in the order specified above. a. Synthesizer Configuration Register I and II: Set VCO center frequency. b. Crystal Control Register: Set TXDATA polarity. c. VCO Control Register: Set VCO tuning range and charge pump output current. Step 5: Set IC to TX mode. For internal mode operation, set Mode Select Register to 0x05E5. For external mode operation, set Pin 24, MODSEL1 to "logic 1", Pin 20, MODSEL0 to "logic 0" and set Mode Select Register to 0x05A5. Whenever frequency is to be changed, or system error has been detected (by reading from the Status Register) the IC must be reset by repeating step 2, 3, 4-a, and 5.
For Receiver Operation Step 1: Supply DC voltage to Pin 23, VIN. Step 2: Set Pin 20, MODSEL0 and Pin 24, MODSEL1 to logic 0 (ground) to ensure the IC is operating in external sleep mode after reset. Step 3: Reset IC by setting Pin 18, SPI_CLOCK and Pin 19, SPI _LATCH to logic high simultaneously for more than 1 us. Step 4: Setup IC's internal control registers by configuring the followings: Synthesizer Configuration Register I, Synthesizer Configuration Register II, VCO Control Register, RX Control Register, and the Mode Select Register. All registers should be written to in the order specified above. a. Synthesizer Configuration Register I and II: Set VCO center frequency. b. VCO Control Register: Set VCO tuning range and charge pump output current. c. RX Control Register: Set mute threshold level, RXDATA mute function and reference voltage for demodulator tank center frequency tuning. When AFC function is used, DM[4:0] must be set to 0x0 for proper operation. Step 5: Set IC to RX mode. For internal mode operation, set Mode Select Register to 0x05F5. For external mode operation, set Pin 24, MODSEL1 to "logic 1", Pin 20, MODSEL0 to "logic 1" and set Mode Select Register to 0x05B5. Whenever frequency is to be changed, or system error has been detected (by reading from the Status Register) the IC must be reset by repeating step 2, 3, 4-a, and 5. (2) Manual calibration: Please see application note (AN_CAL_A7101) for detail description.
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A7101 Application Circuit
C26 NC R14 0 C22 56p C20 NC C19 27p R13 68K L1 4.7u R12 C25 NC C23 1n C18 1n TP1 C24 C21 10n VDD R2 NC 46 45 44 48 47 43 42 41 NC R11 30K TP2 4.7K
U1
R9 LIM2INN LIM2INP LIM1OUT LIM1INN LIM1INP 36 35 34 33 32 31 30 C12 29 C11 28 27 26 25 100n R4 100K R5 0 R6 82K C10 56p TP3 C9 NC J1 CON16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MODSEL1(option) MODSEL0(option) VIN EN_REG(option) SPI_LATCH SPI_CLOCK SPI_DATA GND LVOUT(option) LD(option) GND TXDATAIN MUTE(option) EN_AFC(option) XTALOUT(option) RXDATA 5.6p + C13 10u/16V C15 10n C17 10n 330 CF2 1 2 3 SK107MA R8 330 CF1 1 2 3 SK107MA C14 10n C16 10n
38 RSSI
40
EN_AFC
CAP2_AFC
CAP1_AFC
CAP3_AFC
CMPVIP
LPFINN
LPFINP
39
LPFOUT
TANK1
VDD C1 1 100n ANTENNA R1 U2 2 OUT BPF IN 1 C4 1n 5 6 7 C29 470P R20 10K X1 12M C33 C28 22p C30 30p R21 3.9K 100n C5 47p C6 100p 8 9 10 11 12 100K 1% 2 3 4 VDD_A RXDATA BR_RX NC RFIO BP_BUF
TXDATAIN XTAL1 XTAL2 XTALOUT CAPSW
A7101
TANK2
MUTE MIXOUT VDD_VCO BP_VCO VT BR_VCO CHPOUT
37
R7
82
VDD
SPI_CLOCK
SPI_DATA
MODSEL0
13
14
15
16
17
18
19
20
21
22
23
VDD TP4 C7 100n C27
10u 16V
R18 75K
24
MODSEL1
BP_REG VDD_D LVOUT VOUT LVIN
SPI_LATCH
LD
EN_REG
REGFB
VIN
C31 100p C8 100n
R19 100K
Figure 10. Application Circuit for Transceiver (Data rate = 64Kbps)
C3
10p
C5 C1
20p
R2
68K L1
5.6p 4.7u
R3 C4 1n TP1 TP2 C2 10n R4 30K C7 1n 680
U1
R6 LIM2INN LIM2INP LIM1OUT LIM1INN LIM1INP 36 35 34 33 32 31 30 C12 29 C18 28 27 26 25 R13 47K C27 20p 10n R11 100K R12 1K 100n R9 1M C19 20p R29 18K C14 10n C11 10n C13 10n 470 CF1 1 2 3 IF FILTER R7 470 C16 R30 10n 62K C26 10p C15 10n
40
47
43
48
42
46
45
44
41
39
EN_AFC
CAP2_AFC
CAP1_AFC
CAP3_AFC
CMPVIP
LPFINP
LPFINN
RSSI
38
LPFOUT
TANK1
VDD C10 1 RXDATA R5 100n 100K 1% 2 3 4 1 ANTENNA 7 8 C20 22p X1 12M C21 68p 9 10 11 12 TRX_OUT C9 10n 5 6 VDD_A RXDATA BR_RX NC RFIO BP_BUF TXDATAIN XTAL1 XTAL2 XTALOUT CAPSW
TANK2
MUTE
37
R8 82 C17 10U/16V
VDD
A7101
MIXOUT VDD_VCO BP_VCO VT BR_VCO CHPOUT
SPI_CLOCK
SPI_DATA
MODSEL0
100n 13 14 VDD 15 16 17 18 19 20 21 22 23 24
VIN
C22
MODSEL1
BP_REG VDD_D LVOUT VOUT LVIN
SPI_LATCH
LD
EN_REG
REGFB
C25 470p J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CON15
C23 100n
C24 10u/16V
R17 NC R16 NC C28 100n RXDATA
VIN EN_REG SPI_LATCH SPI_CLOCK SPI_DATA LVOUT LD(option) TXDATA MUTE EN_AFC XTALOUT RXDATA GND
Figure 11. Application Circuit for Transceiver (Data rate = 250Kbps)
PRELIMINARY
(March 2004, Version 0.4)
18
AMIC Technology, Corp.
A7101
C26 NC R14 0 C22 56p C20 NC C19 27p R13 68K L1 4.7u R12 C25 NC C23 1n C18 1n TP1 C24 C21 10n VDD R2 NC 48 42 47 43 41 46 45 44 NC R11 30K TP2 4.7K
U1
R9 LIM2INN LIM2INP LIM1OUT LIM1INN LIM1INP 36 35 34 33 32 31 30 C12 29 C11 28 27 26 25 10n R4 100K R5 0 R6 56K C10 220p TP3 C9 NC J1 CON16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MODSEL1(option MODSEL0(option VIN EN_REG(option) SPI_LATCH SPI_CLOCK SPI_DATA GND LVOUT(option) LD(option) GND TXDATAIN MUTE(option) EN_AFC(option) XTALOUT(option RXDATA 22p + C13 10u/16V C15 10n C17 10n 330 CF2 1 2 3 SK107MA R8 330 CF1 1 2 3 SK107MA C14 10n C16 10n
38 RSSI
40
39
LPFOUT
TANK1
EN_AFC
CAP2_AFC
CAP1_AFC
CAP3_AFC
CMPVIP
VDD C1 1 100n ANTENNA R1 U2 2 OUT BPF IN 1 C4 0.1u 5 6 7 C29 470P R20 10K X1 12M C33 C28 NC C30 47p R21 NC 100n C5 47p C6 100p 8 9 10 11 12 100K 1% 2 3 4 VDD_A RXDATA BR_RX NC RFIO BP_BUF
TXDATAIN XTAL1 XTAL2 XTALOUT CAPSW
A7101
LPFINN
LPFINP
TANK2
MUTE MIXOUT VDD_VCO BP_VCO VT BR_VCO CHPOUT
37
R7
82
VDD
SPI_CLOCK
SPI_DATA
MODSEL0
13
14
15
16
17
18
19
20
21
22
23
VDD TP4 C7 100n C27
10u 16V
R18 75K
24
MODSEL1
BP_REG VDD_D LVOUT VOUT LVIN
SPI_LATCH
LD
EN_REG
REGFB
VIN
C31 100p C8 100n
R19 100K
Figure 12. Application Circuit for Receiver
PRELIMINARY
(March 2004, Version 0.4)
19
AMIC Technology, Corp.
A7101 Ordering Information
Part No. A71P024P01Q Package QFN 48L
PRELIMINARY
(March 2004, Version 0.4)
20
AMIC Technology, Corp.
A7101
Package Information
QFN 48L (7 x 7mm) Outline Dimensions
aaa C
unit: inches/mm
B
D D1
A
E
E1
C
C L b A1 A3 Detail B See Detail B
C
D
0.05 C
A A2
Seating Plane
bbb M C A B
D2
A
A2
E2
See Detail A
0.6max b Detail A e
Symbol
A A1 A2 A3 b D D1 D2 E E1 E2 e L aaa bbb
Dimensions in inches Min 0.031 0.000 0.007 Nom 0.033 0.001 0.026 0.008 0.009 0.276 BSC 0.266 BSC 0.089 0.185 0.276 BSC 0.266 BSC 0.089 0.012 0 0.185 0.020 BSC 0.016 0.020 12 0.010 0.004 0.207 0.207 Max 0.039 0.002 0.039 0.012
Dimensions in mm Min 0.80 0.00 0.18 Nom 0.85 0.02 0.65 0.20 0.23 7.00 BSC 6.75 BSC 2.25 4.70 7.00 BSC 6.75 BSC 2.25 0.30 0 4.70 0.5 BSC 0.40 0.50 12 0.25 0.10 5.25 5.25 Max 1.00 0.05 1.00 0.30
PRELIMINARY
(March 2004, Version 0.4)
21
AMIC Technology, Corp.
0.6max
b
D

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